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note: for detailed information on purchasing options, contact your local allegro field applications engineer or sales representative. allegro microsystems, inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no respon - sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. recommended substitutions: for existing customer transition, and for new customers or new appli - cations, refer to the a6279. 8-bit serial input constant-current latched led driver a6275 date of status change: november 1, 2010 deadline for receipt of last time buy orders: april 30, 2011 this part is in production but has been determined to be last time buy. this classification indicates that the product is obsolete and notice has been given. sale of this device is currently restricted to existing customer applications. the device should not be purchased for new design applications because of obsolescence in the near future. samples are no longer available. last time buy
description the a6275 is specifically designed for led display applications. each bicmos device includes an 8-bit cmos shift register, accompanying data latches, and eight npn constant-current sink drivers. the cmos shift register and latches allow direct interfacing with microprocessor-based systems. with a 5 v logic supply, typical serial data-input rates are up to 20 mhz. the led drive current is de ter mined by the user selection of a single resistor. a cmos serial data output permits cascade connections in applications requiring additional drive lines. for inter-digit blanking, all output drivers can be disabled with an enable input high. a similar 150 ma output device is available as the a6277; a similar 16-bit device is available as the a6276. two package styles are provided: a through-hole dip (suffix a) and a surface-mount soicw (suffix lw). under normal applications, copper leadframes and low logic-power dissipation allow these devices to sink maximum rated current through all outputs continuously over the operating temperature range (90 ma, 0.9 v drop, 85c). both packages are lead (pb) free, with 100% matte tin leadframe plating. 26185.200f features and benefits ? up to 90 ma constant-current outputs ? undervoltage lockout ? low-power cmos logic and latches ? high data-input rate ? pin-compatible with tb62705cp 8-bit serial input constant-current latched led driver packages functional block diagram not to scale a6275 16-pin dip (a package) 16-pin soicw (lw package) mos bipolar ground latch enable output enable (active low) serial data out clock serial data in serial-parallel shift register latches v dd logic supply r ext out 0 out 1 dwg. fp-013-3 out 2 out n i regulator o uvlo
serial-input constant-current latched led driver with open led detection and dot correction a6275 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com selection guide part number package packing ambient temperature (c) a6275ea-t 16-pin dip 25 per tube ?40 to 85 A6275ELWTR-T 16-pin soicw 1000 per reel a6275slwtr-t 16-pin soicw 1000 per reel ?20 to 85 absolute maximum ratings* characteristic symbol notes rating units supply voltage v dd 7.0 v input voltage range v i ?0.4 to v dd + 0.4 v output voltage range v o ?0.5 to v dd + 17 v output current i o 90 ma ground current i gnd 750 ma operating ambient temperature t a range e ?40 to 85 oc range s ?20 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc *these cmos devices have input static protection (class 2) but are still sus cep ti ble to damage if exposed to extremely high static electrical charges. thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value units package thermal resistance r ja package a, 4-layer pcb based on jedec standard 38 oc/w package lw, 4-layer pcb based on jedec standard 48 oc/w *additional thermal information available on the allegro website. 25 50 75 100 125 150 temperature (c) power dissipation, p d (mw) 3500 3250 3000 2750 2500 2250 2000 1750 1500 1250 1000 750 500 250 0 power dissipation versus ambient temperature (r q ja = 38 oc/w) package a (r q ja = 48 oc/w) package lw
serial-input constant-current latched led driver with open led detection and dot correction a6275 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com t u o a t a d l a i r e s n i a t a d l a i r e s d n a k c o l c latch enable output enable (active low) dwg. ep-010-11 in v dd dwg. ep-010-12 in v dd dwg. ep-010-13 in v dd truth table serial shift register contents serial latch latch contents output output contents e l b a n e e l b a n e a t a d k c o l c a t a d input input i 1 i 2 i 3 ... i n-1 i n output input i 1 i 2 i 3 ... i n-1 i n input i 1 i 2 i 3 ... i n-1 i n hhr 1 r 2 ... r n-2 r n-1 r n-1 llr 1 r 2 ... r n-2 r n-1 r n-1 xr 1 r 2 r 3 ... r n-1 r n r n xxx...x x x l r 1 r 2 r 3 ... r n-1 r n p 1 p 2 p 3 ... p n-1 p n p n hp 1 p 2 p 3 ... p n-1 p n lp 1 p 2 p 3 ... p n-1 p n x x x ... x x h h h h ... h h l = low logic (voltage) level h = high logic (voltage) level x = irrelevant p = present state r = previous state v dd dwg. ep-063-6 out
serial-input constant-current latched led driver with open led detection and dot correction a6275 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics at t a = +25c, v dd = 5 v (unless otherwise noted). limits characteristic symbol test conditions min. typ. max. unit supply voltage range v dd operating 4.5 5.0 5.5 v undervoltage lockout v dd(uv) v dd = 0 5 v 3.4 ? 4.0 v output current i o v ce = 0.7 v, r ext = 250 64.2 75.5 86.8 ma (any single output) v ce = 0.7 v, r ext = 470 34.1 40.0 45.9 ma output current matching ? i o 0.4 v v ce(a) = v ce(b) 0.7 v: (difference between any r ext = 250 ? 1.5 6.0 % two outputs at same v ce ) r ext = 470 ? 1.5 6.0 % output leakage current i cex v oh = 15 v ? 1.0 5.0 a logic input voltage v ih 0.7v dd ? v dd v v il gnd ? 0.3v dd v serial data out v ol i ol = 500 a ? ? 0.4 v voltage v oh i oh = -500 a 4.6 ? ? v input resistance r i enable input, pull up 150 300 600 k latch input, pull down 100 200 400 k supply current i dd(off) r ext = open, v oe = 5 v ? 0.8 1.4 ma r ext = 470 , v oe = 5 v 3.5 6.0 8.0 ma r ext = 250 , v oe = 5 v 6.5 11 15 ma i dd(on) r ext = 470 , v oe = 0 v 5.0 10 14 ma r ext = 250 , v oe = 0 v 8.0 16 24 ma typical data is at v dd = 5 v and is for design information only.
serial-input constant-current latched led driver with open led detection and dot correction a6275 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com recommended operating conditions characteristic symbol conditions min. typ. max. unit supply voltage v dd 4.5 5.0 5.5 v output voltage v o ? 1.0 4.0 v output current i o continuous, any one output ? ? 90 ma i oh serial data out ? ? -1.0 ma i ol serial data out ? ? 1.0 ma logic input voltage v ih 0.7v dd ? v dd + 0.3 v v il -0.3 ? 0.3v dd v clock frequency f ck cascade operation ? ? 10 mhz switching characteristics at t a = 25c, v dd = v ih = 5 v, v ce = 0.4 v, v il = 0 v, r ext = 470 , i o = 40 ma, v l = 3 v, r l = 65 , c l = 10.5 pf. limits characteristic symbol test conditions min. typ. max. unit propagation delay time t phl clock-out n ? 350 1000 ns latch-out n ? 350 1000 ns enable-out n ? 350 1000 ns clock-serial data out ? 40 ? ns propagation delay time t plh clock-out n ? 300 1000 ns latch-out n ? 300 1000 ns enable-out n ? 300 1000 ns clock-serial data out ? 40 ? ns output fall time t f 90% to 10% voltage 150 350 1000 ns output rise time t r 10% to 90% voltage 150 300 600 ns
serial-input constant-current latched led driver with open led detection and dot correction a6275 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com timing requirements and specifications (logic levels are v dd and ground) serial data present at the input is transferred to the shift register on the logic 0-to-logic 1 transition of the clock input pulse. on succeeding clock pulses, the registers shift data in- formation towards the serial data output. the serial data must appear at the input prior to the rising edge of the clock input waveform. information present at any register is transferred to the respective latch when the latch enable is high (serial-to- s a a t a d w e n t p e c c a o t e u n i t n o c s e h c t a l e h t . ) n o i s r e v n o c l e l l a r a p e r e h w s n o i t a c i l p p a . h g i h d l e h s i e l b a n e h c t a l e h t s a g n o l the latches are bypassed (latch enable tied high) will l a i r e s g n i r u d h g i h e b t u p n i e l b a n e t u p t u o e h t t a h t e r i u q e r data entry. when the output enable input is high, the output sink s e h c t a l e h t n i d e r o t s n o i t a m r o f n i e h t . ) f f o ( d e l b a s i d e r a s r e v i r d is not affected by the output enable input. with the out- put enable input low, the outputs are con trolled by the state . s e h c t a l e v i t c e p s e r r i e h t f o a. data active time before clock pulse (data set-up time), t su(d) ............................. 50 ns b. data active time after clock pulse (data hold time), t h(d) ................................. 20 ns c. clock pulse width, t w(ck) .................................. 50 ns d. n o i t a v i t c a k c o l c n e e w t e b e m i t and latch enable, t su(l) ............................... 100 ns e. latch enable pulse width, t w(l) ...................... 100 ns f. output enable pulse width, t w(oe) ................... 4.5 s note: timing is representative of a 10 mhz clock. sig- . e l b a n i a t t a e r a s d e e p s r e h g i h y l t n a c i f i n max. clock transition time, t r or t f ....................... 10 s clock serial data in latch enable output enable out n dwg. wp-029-1 50% serial data out data data 50% 50% 50% c a b d e low = all outputs enabled p t data 50% p t low = output on high = output off output enable out n dwg. wp-030-1a data 10% 50% phl t plh t high = all outputs disabled (blanked) f t r t 90% f 50%
serial-input constant-current latched led driver with open led detection and dot correction a6275 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com allowable output current as a func tion of duty cycle a package lw package 020 duty cycle in per cent 100 0 dwg. gp-062-5 60 40 20 40 60 100 80 v ce = 2 v v ce = 3 v v ce = 4 v 80 t a = +25c v dd = 5 v r ja = 60c/w 020 duty cycle in per cent 100 0 dwg. gp-062-4a 60 40 20 40 60 100 80 v ce = 2 v v ce = 3 v v ce = 1 v v ce = 4 v 80 t a = +25c v dd = 5 v r ja = 94c/w 020 duty cycle in per cent 100 0 dwg. gp-062-2a 60 40 20 40 60 100 80 v ce = 1 v v ce = 2 v v ce = 3 v v ce = 4 v 80 t a = +50c v dd = 5 v r ja = 94c/w 020 duty cycle in per cent 100 0 dwg. gp-062-3 60 40 20 40 60 100 80 v ce = 2 v v ce = 3 v v ce = 4 v 80 t a = +50c v dd = 5 v r ja = 60c/w
serial-input constant-current latched led driver with open led detection and dot correction a6275 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 020 duty cycle in per cent 100 0 dwg. gp-062a 60 40 20 40 60 100 80 v ce = 1 v v ce = 2 v v ce = 3 v 80 t a = +85c v dd = 5 v r ja = 94c/w v ce = 0.7 v v ce = 4 v allowable output current as a func tion of duty cycle (cont.) a package lw package typical characteristics 020 duty cycle in per cent 100 0 dwg. gp-062-1 60 40 20 40 60 100 80 v ce = 1 v v ce = 2 v v ce = 3 v v ce = 4 v 80 t a = +85c v dd = 5 v r ja = 60c/w 0.5 dwg. gp-063 1.0 2.0 1.5 v ce in volts 0 60 40 20 0 t a = +25c r ext = 500
serial-input constant-current latched led driver with open led detection and dot correction a6275 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com ground register latches 1 2 3 10 11 12 13 15 4 5 6 7 14 16 serial data out logic supply serial data in output enable latch enable clock ck v dd oe out 1 out 2 out 0 out 4 out 6 out 5 out 3 out 7 r ext i regulator l o 8 9 ground register latches 1 2 3 10 11 12 13 15 4 5 6 7 14 16 serial data out logic supply serial data in output enable latch enable clock ck v dd oe out 1 out 2 out 0 out 4 out 6 out 5 out 3 out 7 r ext i regulator l o 8 9 terminal description terminal no. terminal name function 1 gnd reference terminal for control logic. 2 serial data in serial-data input to the shift-register. 3 clock clock input terminal for data shift on rising edge. 4 latch enable data strobe input terminal; serial data is latched with high-level input. 5-12 out 0-7 the eight current-sinking output ter mi nals. 13 output enable when (active) low, the output drivers are enabled; when high, all output driv- ers are turned off (blanked). 14 serial data out cmos serial-data output to the following shift-register. 15 r ext an external resistor at this terminal establishes the output current for all sink drivers. 16 supply (v dd ) the logic supply voltage (typically 5 v). package a pin-out diagrams package lw
serial-input constant-current latched led driver with open led detection and dot correction a6275 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the load current per bit (i o ) is set by the external re sis tor (r ext ) as shown in the gure below. 300 500 700 1 k 2 k current-control resistance, r ext in ohms 100 0 100 dwg. gp-061 5 k 200 3 k 20 40 60 80 v ce = 0.7 v package power dissipation (p d ). the maximum al- low able package power dissipation is determined as p d (max) = (150 - t a )/r ja . the actual package power dissipation is p d (act) = dc(v ce i o 8) + (v dd i dd ). when the load supply voltage is greater than 3 v to 5 v, considering the package power dissipating limits of these devices, or if p d (act) > p d (max), an external voltage re- ducer (v drop ) should be used. load supply voltage (v led ). these devices are de- signed to operate with driver voltage drops (v ce ) of 0.4 v to 0.7 v with led forward voltages (v f ) of 1.2 v to 4.0 v. if higher voltages are dropped across the driver, package power dissipation will be increased signi cantly. to minimize package power dissipation, it is rec om - mend ed to use the lowest possible load supply voltage or to set any series dropping voltage (v drop ) as v drop = v led - v f - v ce with v drop = i o r drop for a single driver, or a zener diode (v z ), or a series string of diodes (approximately 0.7 v per diode) for a group of drivers. if the available voltage source will cause unacceptable dissipation and series resistors or diode(s) are undesirable, a regulator such as the sanken series sai or series si can be used to pro vide supply voltages as low as 3.3 v. for reference, typical led forward voltages are: white 3.5 ? 4.0 v blue 3.0 ? 4.0 v green 1.8 ? 2.2 v yellow 2.0 ? 2.1 v amber 1.9 ? 2.65 v red 1.6 ? 2.25 v infrared 1.2 ? 1.5 v pattern layout. this device has a common logic-ground and power-ground terminal. if ground pattern layout con tains large common-mode resistance, and the voltage between the system ground and the latch enable or clock terminals ex ceeds 2.5 v (because of switching noise), these devices may not operate correctly. dwg. ep-064 v led v drop v f v ce applications information
serial-input constant-current latched led driver with open led detection and dot correction a6275 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package a 16-pin dip 2 19.050.25 5.33 max 0.46 0.12 1.27 min 1 16 a dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area 6.35 +0.76 ?0.25 3.30 +0.51 ?0.38 10.92 +0.38 ?0.25 1.52 +0.25 ?0.38 0.38 +0.10 ?0.05 7.62 2.54 for reference only (reference jedec ms-001 bb) dimensions in inches, metric dimensions (mm) in brackets, for reference only package lw 16-pin soicw 9.50 0.65 2.25 1.27 c seating plane 1.27 0.25 0.20 0.10 0.41 0.10 2.65 max 10.300.33 7.500.10 4 4 0.27 +0.07 ?0.06 0.84 +0.44 ?0.43 10.300.20 c 0.10 16x 2 1 16 gauge plane seating plane for reference only dimensions in millimeters (reference jedec ms-013 aa) dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area a b reference pad layout (reference ipc soic127p1030x265-16m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances b pcb layout reference view 2 1 16 copyright ?2000-2008, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com

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